============================================================== Guild: wafer.space Community Channel: Information / general / 3.3V SRAM After: 10/31/2025 23:59 Before: 12/01/2025 00:00 ============================================================== [11/17/2025 07:16] urish [11/17/2025 07:16] urish Congrats Tim! [11/17/2025 07:16] urish How many bits? 300x300 will make it useful for TT projects [11/17/2025 07:28] 246tnt 512 bytes AFAIR {Reactions} ๐Ÿ‘ [11/17/2025 14:42] rtimothyedwards_19428 512 bytes was the largest of the four GF 5V SRAM macros. I was thinking of expanding that to 1kB for another macro; shouldn't be too hard. But I'll get this one done first. [11/17/2025 15:04] rtimothyedwards_19428 @urish : What size is a TT slot on GF180MCU? [11/17/2025 15:06] 246tnt 346.64 um x 160.72 um [11/17/2025 15:06] urish https://github.com/TinyTapeout/tt-support-tools/blob/main/tech/gf180mcuD/tile_sizes.yaml {Embed} https://github.com/TinyTapeout/tt-support-tools/blob/main/tech/gf180mcuD/tile_sizes.yaml tt-support-tools/tech/gf180mcuD/tile_sizes.yaml at main ยท TinyTape... Tiny Tapeout project build tools + chip integration scripts - TinyTapeout/tt-support-tools [11/17/2025 15:07] 246tnt But that means in a 2x2 ( 711.20 um x 325.36 um ) you can fit a decent size SRAM and some logic. {Reactions} ๐Ÿ‘ [11/17/2025 23:13] rtimothyedwards_19428 The SRAM block is now both DRC and LVS clean. I will work tomorrow on squeezing out additional space at the bottom and then I will push to the repository. Again, don't expect timing values at this point in the process. {Reactions} blobclap (2) ๐ŸŽ‰ (3) [11/18/2025 02:29] mithro_ @Tim Edwards - Super cool! [11/18/2025 18:27] rtimothyedwards_19428 First commit of the 3.3V SRAM (512 bytes) is now *LIVE* at https://github.com/RTimothyEdwards/gf180mcu_ocd_ip_sram/ ! {Embed} https://github.com/RTimothyEdwards/gf180mcu_ocd_ip_sram/ GitHub - RTimothyEdwards/gf180mcu_ocd_ip_sram: 3.3V SRAM macros for... 3.3V SRAM macros for GF180MCU, based on the original 5V SRAM macros. - RTimothyEdwards/gf180mcu_ocd_ip_sram 2025-11_media/gf180mcu_ocd_ip_sram-C0677 {Reactions} ๐ŸŽ‰ ๐Ÿ‘ [11/19/2025 00:30] mithro_ @Tim Edwards - Awesome work! [11/19/2025 00:31] mithro_ What's `ocd`? [11/19/2025 01:31] rtimothyedwards_19428 Open Circuit Design (or Obsessive-Compulsive Disorder; take your pick). [11/19/2025 22:34] rtimothyedwards_19428 Pushed an update today. I managed to squeeze some space out of it, but not as much as I originally thought I could; ultimately I recovered about 8um which is not terribly useful for having spent a full day and a half doing it. The final layout area is 301.3um x 321.89um. The fact that the height is now less than a TT slot height is purely coincidental, and probably meaningless. All digital pinouts are on the bottom side and there is only enough space in the TT slot to get maybe 9 routes in from the side, whereas the block has 36 digital I/O. It could be rotated 90 degrees but then the I/O are not in the preferred direction. [11/19/2025 22:35] mithro_ @Tim Edwards - How does that compare to the 5V SRAM? [11/20/2025 00:50] rtimothyedwards_19428 Area-wise, it's slightly less than 1/2 the area. [11/20/2025 06:45] 246tnt @Tim Edwards Well it would be easy enough to make a thin wrapper that brings the traces to the preferred routing direction ( and possibly adapts power rails so they connect nicely too ). [11/20/2025 17:24] rtimothyedwards_19428 I thought about that but didn't do a feasibility study. : ) Yet. Also: It's pretty easy to make the smaller SRAM versions, since GF used the same control block exactly, just removed a number of rows and grounded the upper address bits. The 256 byte SRAM is 301.3um x 224.93um. It took me less than 30 minutes to create the 256 byte layout from the 512 byte layout, but there are a couple of LVS errors I need to fix. I should be able to get that pushed before the end of the weekend. [11/20/2025 22:02] mithro_ :joke: Shouldn't it be 1/4th the size? ๐Ÿ˜› [11/20/2025 22:24] rtimothyedwards_19428 The transistors scale to 1/4 area; everything else, not so much. [11/20/2025 22:26] mithro_ Yeah, sadly I knew that [11/21/2025 22:50] rtimothyedwards_19428 I have pushed the 256 byte SRAM as well (now DRC and LVS clean). {Reactions} ๐ŸŽ‰ (2) [11/22/2025 08:56] 246tnt @Tim Edwards Do you have a test slot planned for those ? Because I would love to have those validated in the first run, along with the split voltage IO lib since I'm planning to use those for the second tiny tapeout run ( and hopefully we'll have the results of the first run by then ). [11/22/2025 15:08] urish Thought on putting them on TTGF0p2? [11/22/2025 15:10] rtimothyedwards_19428 @tnt : That was my plan. I should be able to get something out in a week. It won't be a very complex chip but I should be able to put together a simple "openframe" version of Caravel-GF using the mixed-voltage pads and drop some SRAMs in the middle along with some basic control logic and call it a day. [11/22/2025 15:11] rtimothyedwards_19428 @urish : Maybe? What's the current support for 3.3V on TTGF? [11/22/2025 15:15] urish TTGF runs in 3v3 by default [11/22/2025 15:16] urish The main question is if we feel confident enough to put it since designs aren't power gated [11/22/2025 15:18] 246tnt @urish Well not really because there aren't power gates and I'd like to run comparison between 3.3v and 5v which means everything on there must support 5V without destroying the chip ... [11/22/2025 15:23] urish And I guess the SRAM isn't 5v tolerant? [11/22/2025 15:25] 246tnt Well ... it's in the title, it's a 3.3V SRAM with all the transistors resized from 5V to 3.3V ๐Ÿ˜… [11/22/2025 15:25] 246tnt I mean weather it would burst in flames at 5V ... probably not tbh. [11/22/2025 15:29] rtimothyedwards_19428 I don't know the breakdown voltage for 3.3V transistors offhand. [11/22/2025 15:37] 246tnt Punch-Through Voltage in the spec is 6.5V min [11/22/2025 15:37] 246tnt (from https://gf180mcu-pdk.readthedocs.io/en/latest/analog/spice/elec_specs/elec_specs_1.html ) [11/22/2025 16:40] urish So should be fine then? [11/22/2025 16:52] 246tnt I guess so, to some extent ... [11/22/2025 17:38] urish It's your call [11/23/2025 23:24] mithro_ Two thoughts: * I have offered Tim Edwards a slot... * I'm open to Tiny Tapeout using multiple slots, there should be some spare. {Reactions} ๐Ÿ‘ [11/24/2025 05:22] urish Thanks Tim! [11/24/2025 05:22] urish Re using multiple slots - that's up to Sylvain [11/30/2025 18:06] rtimothyedwards_19428 Currently working through DRC errors as seen by klayout on the SRAM blocks. It's a bit tedious but no major issues. ============================================================== Exported 44 message(s) ==============================================================